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BackHardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical.kicad_mod Normal file Unescape top_margin = (board_height - hole_vdist) / 2; standoff_radius = hole_radius * 2.5; Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # Netlist files (exported from Eeschema # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 16561 bytes 3D Printing/Rails/36hp_innie.stl | Bin 0 -> 11675 bytes .../Panels/FIREBALL VCO.png | Bin 0 -> 87811 bytes sr1_full.png | Bin 0 -> 12821 bytes .../Panels/COLOR SPRAY.png | Bin 0 -> 38860 bytes Panels/futura.
- -8.171747e-001 0.000000e+000 vertex 4.735710e+000.
- Normal -0.0702817 -0.382543 0.921261 facet normal 0.0570302 0.0726013.