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BackSubmodule init git submodule update ``` ``` git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git ``` 4d5fa6d903 Delete 'Panels/futura medium condensed bt.ttf' 16055f0ae5 Delete 'Panels/futura medium bt.ttf' Panels/futura medium condensed bt.ttf' ## Current draw ### Current draw PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Features already done: - Internal clock with manual control. Clock in socket with amplifier to handle weaker (<6v) signals - Clock POT is the first foreach($imgs as $img){ $article['content'] .= "
" . $entry->textContent . "
"; } } Invisible Bread, Softer World (alt tags), Dinosaur Comics Cleanup elseif (strpos($article['content. New Pull Request