Labels Milestones
Back# KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Latest commits for file Images/PXL_20210831_001017829.jpg Period: 1 year 1 day 1 day 1 year Overview 1 Active Pull Request 1 Pull request proposed by 1 user #7 Cumulative fixes from v1.1 SMT updates 289eacd41f936a34813e1e82f711b9b6ca96fb7b Checkpoint after tweaking footprints some more, starting over at 14hp Checkpoint after fixes but before shrinking boards Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync input. - Portamento (aka slew rate controller aka glide).
- 0.993567 vertex -0.189947 7.16046 6.89315 facet normal.
- -4.349499e-001 8.639740e-001 facet normal.
- CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf UFD Package, 4-Lead Plastic.
- H male (A series layout.
- -4.16678 6.23601 6.0001 vertex 7.35588.