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Back*-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= 9060b76361734f9abf9a1c676dd9110e9ced917b Add MK manuals e49f4ab127 Add Kick as separate sheet initial kicad project .../OttosIrresistableDance.kicad_pcb | 2 | | | R4, R12, R13 | 3 | 100R | Resistor | | | | | | | | | S1 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm 2x5"/>