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From 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Mon Sep 17 00:00:00 2001 Subject: [PATCH] submodule update Find and replace last few thin traces, fix teardrops and gnd fill f63cfba954 Embiggen traces, add teardrops f63cfba9541079f9f5e1341fca38abad6837ea65 Add 55k-ish resistor to coarse knob to fix tuning range Add 55k-ish resistor to coarse knob to fix tuning range updates the potentiometer pads and trace routing to de-bodge the pots. 6523065365c12ceda76dbda25c5041018c73eb63 's notes on updating the two clockwise-most pins, looking from below. Clock rate goes down when resistance goes up, opposite to expectation. Glide fix Notes from MK's PCB livestream Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png and /dev/null differ QuentinEF.ttf Normal file View File 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/SPIDER CLIMB.png differ Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/MIRROR IMAGE.png Normal file Unescape "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Name": "Bottom Silk Screen" "Name": "Top Silk Screen" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Name": "Bottom Solder Mask" "Name": "Bottom Silk Screen" "Name": "Top Solder Paste" "Name": "Bottom Solder Paste" "Name": "Bottom Silk Screen" "Name": "Top Silk Screen" "Name": "Top Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIN5.kicad_mod Normal file Unescape 3D Printing/Pot_Knobs/scaled_french_pot.mix cube([board_width, board_height, thickness]); linear_extrude(thickness) polygon([[0,0], [(board_width-insert_width)/2, -insert_depth], [board_width-(board_width-insert_width)/2, -insert_depth], [board_width, 0]]); Update 'Samba Reggae 1' a704d3e530 More traces and vias, and net links Add four more switches/buttons, move LED drivers onto PCB added the once through idea with commentary by Correcting changed filename in .prl 54f1a61ba5 gets jiggy with PCB trace layout created pull request 'pcb_finalization' (#1) from bugfix/10hp into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request synth_mages/MK_VCO#7 7#Cumulative fixes from v1.1 Checkpoint after tweaking footprints some more, starting over at 14hp PCB initial layout, no traces Fireball/Fireball.kicad_prl.

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