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# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= 2dd0b8c0c736720a0b064bbe1304dc9562beb260 init 2dd0b8c0c736720a0b064bbe1304dc9562beb260 init 2dd0b8c0c736720a0b064bbe1304dc9562beb260 init 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version Add html test version Samurai Latest commits for file Panels/title_test_22.stl

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