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Temporary files *.000 *.bak Initial version *.dsn *.ses Fireball/Fireball VCO saw wave core.circuitjs.txt Latest commits for file Panels/FireballSpellVertSmall.png From bacdac34d747275148c56e8293dc209c2e326fe4 Mon Sep 17 00:00:00 2001 .../Panels/POLYMORPH.png | Bin 0 -> 86371 bytes rename LUTHERS_VCO.diy => Schematics/LUTHERS_VCO.diy (100% create mode 100644 Hardware/PCB/precadsr/precadsr.kicad_pro create mode 100644 Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Cu.gbr create mode 100644 Synth_Manuals/LABOR_MANUAL.pdf create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod delete mode 100644 Fireball/Fireball.kicad_prl create mode 100644 Panels/luther_triangle_vco_quentin_v2.scad create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-08A_1x08_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod create mode 100644 Images/IMG_6777.JPG MK_VCO/Fireball/Fireball VCO saw wave core.circuitjs.txt Fireball/fp-info-cache Normal file Unescape Latest commits for file Datasheets/2N3903-Motorola.pdf # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-NPTH.drl Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro Normal file View File Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.drl Normal file View File Panels/FireballSpell.png Executable file View File 3D Printing/Pot_Knobs/18-spline-pot-knob-no-indicator-line.stl Executable file View File # Format documentation: https://kicad.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak Initial kicad, images, gitignore for kicad backups Initial kicad, images, gitignore for kicad backups .gitignore | 16 Docs/precadsr_bom.md | 72 Hardware/PCB/precadsr/potsetc.sch | 663 Hardware/PCB/precadsr/precadsr.net | 147 Hardware/PCB/precadsr/precadsr.pro | 22 Panels/title_test.stl | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 38860 bytes Panels/futura medium bt.ttf | Bin 0 -> 461484 bytes Panels/title_test_36.stl .

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