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Wants to merge 5 commits from bugfix/v1.1 into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp eb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file tstamp 1c9c2c29-57db-4a4e-bbff-29f893ea0430) Final revision; added custom DRC as project file tstamp 6b7d6cc6-a11c-4566-a5f2-ddde4d827642) Final revision; added custom DRC as project file tstamp 62e17d71-a82e-47f7-8a14-a0885fbe0008) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track'")) # This would override board outline and milled areas # (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'via' && B.Type == 'track'" (condition "A.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 15:59:21 2021 ac58a9eaed checkpoint after roughing out middle PCB Binary files /dev/null and b/Docs/precadsr.pdf differ main synth_tools/3D Printing/Pot_Knobs/Potentiometer Cap.STL Executable file View File 3D Printing/Cases/Eurorack Modular Case/20210926_092147.jpg Executable file View File 3D Printing/Pot_Knobs/pot_knob-6mm-with-marker.stl Executable file View File 3D Printing/Pot_Knobs/FS_PotiKnob_d6D12h9.stl Executable file View File Panels/FireballSpell_Large_bw.png.svg Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-PTH.drl Normal file Unescape Schematics/SynthMages.pretty/eurorack_rail_hole.kicad_mod Normal file Unescape width = 36; // [1:1:84] width = 36; // [1:1:84] width = 12; // Number of faces.

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