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Those Apply jlcpcb's design rules, small fixes for those couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups d7370bb10c Add tl074 datasheet/pinout Binary files /dev/null and b/Panels/FIREBALL VCO.png differ false XS3 FM CV XS2 1V/OCT CV R13 - TUNE R19 - TUNE R19 - TUNE.

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