Labels Milestones
BackB.Cu" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks merged pull request 'Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement Fix rail clearance issues, make all power main synth_tools/Schematics/SynthMages.pretty/Switch.lib 1741 lines main MK_VCO/Panels/FireballSpell.dxf 25135 lines 72 65 73 0 40 Y Y 1 F N DEF SW_DPST_x2 SW 0 0 Y N 1 F N DEF SW_Push_DPDT SW 0 0 vertex -6.36396 -6.36396 3.82299 facet normal 8.550802e-01 5.222628e-03 5.184694e-01 facet normal -0.312676 -0.468065 -0.826528 vertex -1.60745 2.41466 18.8956 facet normal -9.062902e-001 -5.070952e-003 4.226256e-001 vertex 5.052543e+000.
- 06 bottom-side contacts, 1.0mm.
- Connectors, 502430-4010, 40 Pins per row.
- Width 25.4mm Vishay TJ5 BigPads.
- 0.110591 -0.826421 vertex 2.89821.
- Number: 1843347 8A 160V Generic Phoenix Contact.