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*.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'More schematics' (#3) from schematic into main ... Add notes about wiring SW15 cross-board facet normal 0.0819177 0.0822333 -0.993241 facet normal -8.613040e-01 -5.080899e-01 -3.157564e-04 vertex -1.036795e+02 9.542199e+01 1.855000e+01 vertex -1.021770e+02 9.353808e+01 2.655000e+01 facet normal 0.773356 -0.633859 -0.0119696 facet normal 0.192217 0.421013 0.886454 vertex -4.87063 4.68184 7.03353 facet normal 5.357023e-002 9.985641e-001 -0.000000e+000 vertex 7.390471e-001 5.579846e+000 1.747200e+001 facet normal -0.0754507 -0.766031 -0.63836 facet normal 0.768557 0.63056 0.108238 facet normal -9.449638e-01 6.305657e-04 -3.271744e-01 vertex -1.084626e+02 9.695134e+01 1.068604e+01 facet normal 0.290283.

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