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LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Schematics/Enlarge/Enlarge.kicad_pro Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/drill_report.rpt Normal file View File Hardware/PCB/precadsr/precadsr.kicad_sch Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_Power.stl Executable file.

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