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BackNormal -2.848412e-15 -5.571398e-15 1.000000e+00 facet normal -1.041895e-01 2.887251e-03 -9.945533e-01 facet normal -0.39254 -0.734385 0.553707 facet normal 4.784231e-001 8.781294e-001 0.000000e+000 vertex -3.168653e+000 -4.714065e+000 2.496000e+001 vertex -2.840252e+000 6.427855e+000 9.983999e+000 vertex -2.075797e+000 -6.801728e+000 1.747200e+001 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: make power connection traces larger; MK uses a ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s Compare 6 commits » 33729ec97f More repo cleanup, adopt github .gitignore file More repo cleanup, adopt github .gitignore file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane Binary files a/Images/precadsr-panel.png and b/Images/precadsr-panel.png differ From f1ff8406b412e95346ec2837fcbe5f8c2630c4ee Mon Sep 17 00:00:00 2001.
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