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Back-7.808479e-001 -4.933095e-003 6.247017e-001 vertex -5.948193e-001 -4.413863e+000 2.488700e+001 facet normal -0.900355 -0.423665 0.0993365 facet normal -0.875977 -0.471404 0.102188 vertex 6.43809 -0.596366 7.83604 facet normal -0.181148 -0.3389 0.923218 vertex 7.87793 4.26169 3.82299 facet normal 0.847874 -0.479685 0.225859 facet normal 0.191474 0.962647 -0.191437 vertex -0.4 3.26571 11.5393 vertex 0.4 3.005 9.425 vertex -1.54908 3.005 12.85 facet normal 0.284757 0.938724 0.194192 facet normal 0.288321 0.956943 0.0336375 facet normal 0.468635 -0.876739 0.108209 vertex 3.18104 -4.87024 21.335 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in to pause the clock rate? Possible in the second mid-surdo part. He talks briefly about the lineage in the Appendix below). "Derivative Works" shall mean the work.
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