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FM LVL Binary files a/Panels/futura medium bt.ttf Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-job.gbrjob Normal file Unescape ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks merged pull request synth_mages/MK_VCO#1 cfb5bfb128 Finish schematic, add PDF' (#2) from schematic.

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