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0.109224 -0.0703593 vertex 4.76941 8.07987 6.03331 vertex 4.74434 -8.21743 6.17306 vertex 9.99509 0 0.0491305 facet normal -0.435818 -0.815358 0.381123 facet normal -7.808552e-001 -3.477092e-003 6.247024e-001 facet normal 2.635472e-01 4.897575e-03 -9.646341e-01 vertex -1.055399e+02 9.715134e+01 1.037452e+01 vertex -1.051912e+02 9.715134e+01 1.086671e+01 vertex -1.052173e+02 9.695134e+01 1.073430e+01 facet normal -0.114495 -0.30557 0.945261 facet normal -0.0819349 -0.0819588 -0.993262 vertex -3.03604 -4.44467 21.8214 vertex 4.24331 2.97557 21.7998 vertex -4.03376 -2.95564 21.7809 facet normal 0.400414 -0.779905 0.481058 vertex 4.81447 -4.25586 7.51797 vertex 4.78188 -4.20094 7.71954 facet normal -0.956943 -0.288321 0.0336375 facet normal -2.614944e-15 -7.910530e-01 6.117476e-01 facet normal -0.768293 -0.629624 0.115323 vertex 3.43619 3.13874 21.7467 facet normal -4.487522e-001 -7.874047e-001 4.226290e-001 vertex 7.392447e-001 5.353779e+000 2.475471e+001 facet normal 4.136177e-01 -2.108080e-03 -9.104482e-01 vertex -1.084728e+02 9.695134e+01 1.262749e+01 facet normal 9.094768e-001 4.157546e-001 0.000000e+000 facet normal -0.630721 -0.768426 0.108223 facet normal -7.636917e-01 -2.438923e-03 6.455765e-01 vertex -1.046824e+02 9.695134e+01 9.503409e+00 vertex -1.046252e+02 9.725134e+01 9.572266e+00 facet normal -3.318474e-001 5.689107e-001 7.524745e-001 vertex 2.813232e+000 -3.197688e+000 2.491820e+001 facet normal 8.712699e-01 -4.908041e-01 -3.185965e-04 vertex -9.102169e+01 9.554692e+01 2.550000e+00 facet normal 0.0922671 0.172963 0.980597 vertex 5.0946 -5.35022 6.88312 facet normal -0.758285 0.622326 0.194199 facet normal -8.031676e-001 -3.367382e-003 5.957437e-001 vertex 5.108496e+000 -2.948792e+000 2.482134e+001 facet normal -0.480608 0.871278 0.0994478 facet normal -0.201286 0.235684 0.950756 facet normal -0.952359 0.288955 0.0975571 vertex -8.82707 1.75581 0 vertex 3.89968 -9.41467 0 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@github.com:holmesrichards/precadsr.git New KiCad version; non Al panel Gerbers polygon (pts Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'via' && B.Type == 'graphic')" (condition "A.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] gets comfier with gitignore and git rm --cache 19116ba39d Apply jlcpcb's design rules, small fixes for those Apply jlcpcb's design rules, small fixes for those couple more GND-stitch vias eb8580ef62 Undo converting GND to GND_JMP and fix everything that broke From 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add tl074 datasheet/pinout Datasheets/tl074-pinout.jpeg | Bin 0 -> 16561 bytes create mode.

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