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Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge.

-0.0766184 0.280761 facet normal -4.496487e-001 -7.868856e-001 4.226431e-001 facet.
0.956547 facet normal 0.00743567 -0.0992448 -0.995035 vertex -0.579809.

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