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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Latest commits for file Panels/FireballSpell.dxf 99b8f1493d Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane on only one cross-board wire is needed, vs 3 if.
- Clear LED, Round, FlatTop.
- (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf 16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad.