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3.014290e+000 2.496000e+001 vertex -1.925954e+000 -5.351777e+000 1.747200e+001 facet normal -0.598691 -0.491338 0.632579 vertex 6.18591 -6.18591 5.33536 facet normal 0.629688 0.768246 0.115285 facet normal -0.29034 -0.956924 -9.5392e-07 facet normal 2.94821e-05 -0.956933 -0.290308 vertex 1.31069 3.16429 11.8737 vertex -0.800782 3.26571 11.5393 vertex -1.45059 3.07081 15.6068 vertex -0.4 3.005 16.275 vertex -1.54908 3.005 9.425 vertex 1.31069 3.16429 16.275 vertex 0.4 -3.00952 6.59 vertex 2.81683 1.16677 6.59 vertex -2.69268 -2.0165 6.59 vertex -1.17054 -5.88471 6.59 vertex -0.4 3.34544 16.275 facet normal 6.453925e-02 2.878077e-03 -9.979110e-01 facet normal -8.051217e-001 5.931096e-001 0.000000e+000 vertex -1.209642e+000 5.491410e+000 2.496000e+001 vertex 1.269793e+000 6.921616e+000 9.983999e+000 vertex -7.050429e+000 -2.769859e-001 9.983999e+000 vertex -4.245195e+000 -5.688466e+000 1.747200e+001 facet normal 3.874184e-001 6.779832e-001 6.246966e-001 vertex -2.733915e+000 -3.191522e+000 2.488700e+001 facet normal 0.0980092 0.995186 3.9263e-06 facet normal 0.555567 -0.831471 1.34063e-06 facet normal -0.768773 -0.630299 0.108219 facet normal -2.497601e-01 -9.683078e-01 0.000000e+00 vertex -9.090385e+01 9.578066e+01 1.855000e+01 vertex -9.259156e+01 1.042646e+02 1.855000e+01 vertex -9.059519e+01 9.652586e+01 3.455000e+01 vertex -1.032503e+02 9.473903e+01 3.455000e+01 vertex -9.129400e+01 9.507470e+01 2.655000e+01 facet normal -0.989341 0.0974419 0.108207 facet normal -0.314934 0.485556 -0.815507 vertex 1.60745 2.41466 18.8956 facet normal 4.639141e-001 8.140082e-001 3.495346e-001 vertex -5.671744e-001 -4.365484e+000 2.480400e+001 facet normal -0.607317 -0.740025 0.289014 vertex -4.98467 -7.46009 4.79464 facet normal -0.550873 0.679084 0.485163 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository https://github.com/holmesrichards/precadsr Submodules git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git ``` 4d5fa6d903 Delete 'Panels/futura medium bt.ttf' From 496e3e33446b55a1a2a83a967e779b5254a33381 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change C13 to 10 nF | Unpolarized capacitor | | | Tayda | A-1847 | | Tayda | A-804 | | J12 | 1 uF | Unpolarized capacitor | | | Tayda | A-4755 | | | | | | | | | | | | | | Tayda | A-804 | | | J3 | 1 From f33ea6a168329cd0061e01c376cbd377f46ddc60 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add ground fills, fix some clearance issues, make all power traces large Added input resistor for sync; placed everything on PCB Added input resistor for sync; placed everything on PCB Added hard sync to schematic, laid out PCB with on-board components PCB initial layout.

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