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BackA19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file polygon (pts New KiCad version; non Al panel Gerbers psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: merged pull request 'More schematics' (#3) from schematic into main created pull request 'Put title box in PDF export' (#4) from schematic into main afea9d5a2c Final revision; added custom DRC as project file tstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with on-board components Added hard sync to schematic, laid out PCB with on-board components Add correct footprints to fireball Merge pull request 'Put title box in PDF export 45cf8c00cd Merge pull request.
- Vertex -5.7853 -4.29641 7.81019 facet normal 1.605954e-001 -2.740493e-001.
- Width 16mm Capacitor C, Rect.