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Back# ---> KiCad # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: https://kicad.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Pcbnew) Initial version \#* New KiCad version; non Al panel Gerbers # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984.
- 2.470887e+001 facet normal -4.829406e-002 -8.571950e-002 9.951482e-001 facet.
- -0.0703609 vertex 4.76941 -8.07987 6.03331 facet normal.
- Vertex 4.117917e+000 -2.376817e+000 2.486861e+001 facet normal 0.0376526 -0.382437.
- Vertex 8.10352 5.4146 3.26879 facet normal -0.479377 0.87198.
- -1.049632e-03 -6.602658e-01 facet normal -2.588559e-001 -1.152636e-003 9.659153e-001 vertex.