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[PATCH] tweaks layout with input from sam 32 "B.Adhes" user "B.Adhesive" (33 "F.Adhes" user "F.Adhesive" (34 "B.Paste" user (35 "F.Paste" user (36 B.SilkS user (37 F.SilkS user hide (37 F.SilkS user hide (37 F.SilkS user hide (0 "F.Cu" signal (31 B.Cu signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 F.Paste user (36 "B.SilkS" user "B.Silkscreen" (37 "F.SilkS" user "F.Silkscreen" (38 "B.Mask" user (39 F.Mask user (40 Dwgs.User user hide (48 B.Fab user (49 F.Fab user (aux_axis_origin 0 0 Y N 1 F N DEF SW_DPDT_x2 SW 0 0 Y N 1 F N DEF 2_pin_Molex_header J 0 40 Y Y 5 N DEF SW_Reed_SPDT SW 0 40 Y N 1 F N DEF SW_DIP_x11 SW 0 20 Y N 1 F N DEF SW_Reed_Opener SW 0 40 Y N 2 F N DEF SW_Coded_SH-7040 SW 0 0 Y N 1 F N DEF SW_SPST SW 0 40 Y N 3 F N DEF SW_DIP_x07 SW 0 40 Y N 1 F N DEF 3_pin_Molex_connector J 0 40 Y N 1 F N DEF SW_Push_45deg SW 0 0 Y N 1 F N DEF Synth_power_2x5 J 0 40 Y N 1 F N DEF SW_Push_Dual SW 0 40 Y N 1 F N DEF SW_Rotary3x4 SW 0 0 PCM_kikit Tab A symbol representing annotation for tab placement Latest commits for file Schematics/LUTHERS_VCO.diy Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm.

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