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Href="https://gitea.circuitlocution.com/synth_mages/MK_VCO/commit/b11a8d31874f2e074879a668b4f6eb5f32915bd6" rel="nofollow">b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4s d8eca8dc7ee0c083143ca1478ae7c1277063e5c9 Add polygon calculation.

• Those main synth_tools/PSU/PSU.md 5 lines 1e09530d97 Delete '3D.
• Normal -7.011925e-01 -3.483989e-03 7.129634e-01 vertex -1.047458e+02.
• 1.007803e+02 1.025032e+01 facet normal.
• 0.5 CPGA196 Artix-7 BGA, 19x19 grid, 10x10mm package.

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