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An edge cut? Corrected in Rev 2.0 alpha 1: Properly assign potentiometer pads and thermal vias; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf WLCSP-49, 7x7 raster, 3.277x3.109mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf LFBGA-144, 12x12 raster, 5.24x5.24mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132 Pins, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32g473pb.pdf ST UFBGA-129, 7.0x7.0mm, 129 Ball, 13x13 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wl54jc.pdf ST UFBGA-121, 6.0x6.0mm, 121 Ball, 11x11 Layout, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf Plastic Small Outline (SO) (http://www.everlight.com/file/ProductFile/201407061745083848.pdf 5-Lead Plastic Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf SSO Stretched SO SOIC 1.27 16 12 Wide 16-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download DFN8 2x2, 0.5P.

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