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BackStuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= b1fcba1e78f37669542b35a3e32a5257c5c0240c c9e81f0cc630cea052574ce7c50b3e82145bb626 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for file Fireball/Fireball.kicad_pcb tweaks layout with input from sam tweaks layout with input from sam Latest commits for file Panels/FIREBALL VCO.png Normal file View File 3D Printing/Panels/SPIDER CLIMB.png and /dev/null differ # 2-layer, 1oz copper condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" condition "A.Type == 'via' && B.Type == A.Type" (condition "A.Type == 'via' .
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