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Pitch, http://www.issi.com/WW/pdf/43-46LQ32256A-AL.pdf Altera BGA-256 M256 MBGA BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf Altera UBGA U324 BGA-324 BGA-624, 25x25 grid, 21x21mm package, pitch 0.8mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.8mm; http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#p495 TFBGA-216, 15x15 raster, 10x10mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf WLCSP-49, 7x7 raster, 3.029x3.029mm package, pitch 0.4mm; http://ww1.microchip.com/downloads/en/devicedoc/atmel-8235-8-bit-avr-microcontroller-attiny20_datasheet.pdf#page=208 WLCSP-16, 1.409x1.409mm, 16 Ball, 4x4 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb55vc.pdf Texas Instruments EUS 5 Pin (https://www.jedec.org/sites/default/files/docs/MO-193D.pdf variant AB), generated with kicad-footprint-generator JST GH series connector, DF3EA-05P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 52 Pin (http://www.holtek.com/documents/10179/116711/HT1632Cv170.pdf), generated with kicad-footprint-generator JST GH series connector, LY20-34P-DT1, 17 Circuits (https://www.molex.com/pdm_docs/sd/2005280170_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py Texas Instruments, DSBGA, area grid, YZT, 1.86x1.36mm, 12 Ball, 3x4 Layout, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/tps63000.pdf 3x3mm Body, 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx Allegro Microsystems 12-Lead (10-Lead Populated) Quad Flat No-Lead Package, 9x9mm Body (see Microchip Packaging Specification 00000049BS.pdf SSOP28: plastic shrink small outline package; 18 leads; body width 4.4 mm; (see NXP sot054_po.pdf TO-126-2, Horizontal, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf TO-251-2 Vertical RM 2.54mm TO-126-3, Vertical, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF TO-262-3 Horizontal RM 1.7mm Pentawatt Multiwatt-5 TO-220-7, Vertical, RM 2.54mm, see http://www.vishay.com/docs/88898/b2m.pdf DIL DIP PDIP 5.08mm 2.54 4-lead dip package with missing pin 5, row spacing 15.24 mm (600 mils), LongPads 16-lead though-hole mounted high-volatge DIP package (based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, based on the quality and performance of the Software. THE SOFTWARE OR THE USE OR PERFORMANCE OF Copyright 2010-2020 Mike Bostock Copyright 2001 Robert Penner Copyright 2016-2021 Mike Bostock Permission to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the work other than copying, distribution and modification are not limited to software source code, documentation source, and configuration files. "Object" form shall.

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