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BackRef="R27" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/60B16110" Ref="J?" Part="1" AR Path="/607ED812/60A9C088" Ref="R30" Part="1" AR Path="/607ED812/60970E37" Ref="S3" Part="1" AR Path="/607ED812/607F01E7" Ref="R109" Part="1" AR Path="/607ED812/607F01E7" Ref="R109" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/60802BB2" Ref="R?" Part="1" AR Path="/607ED812/60A9C096" Ref="R24" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/60970E37" Ref="S?" Part="1" AR Path="/607ED812/60C3833D" Ref="R21" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/607ED812/60C38349" Ref="R23" Part="1" AR Path="/607ED812/60970E37" Ref="S3" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/60802BB2" Ref="R?" Part="1" AR Path="/607ED812/60B16110" Ref="J8" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/607ED812/60802B98" Ref="R29" Part="1" AR Path="/60970E37" Ref="S?" Part="1" AR Path="/607ED812/607F01E7" Ref="R109" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60970E37" Ref="S3" Part="1" AR Path="/607ED812/60802BB2" Ref="R114" Part="1" AR Path="/607ED812/60802BB2" Ref="R31" Part="1" AR Path="/60A9C0A9" Ref="R?" Part="1" AR Path="/609384DB" Ref="#FLG?" Part="1" AR Path="/6091D1B4" Ref="S?" Part="1" AR Path="/6091D1B4" Ref="S?" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/607ED812/6091D1B4" Ref="S3" Part="1" AR Path="/607ED812/60C38349" Ref="R10" Part="1" AR Path="/60A9C096" Ref="R?" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 Subject: [PATCH] A couple more GND-stitch vias Latest commits for file Images/captest.png From 4efd2875e878899162f2c2dc07deaf41da7fb0b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane on only one cross-board wire that shouldn't be over about 20mm in diameter at the first footprint "IDC-Header_2x05_P2.54mm_Vertical_Fixed_Ground_Fill" (version 20221018) (generator pcbnew Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer B.Cu" "Notes": "Layer F.Mask" "Notes": "Layer B.SilkS" .