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Back# Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= 2cddc4d62d38c9e1b69839f92a19e7915eecbceb 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix sr2 blue Fix sr2 blue caixa_sr2.png | Bin 0 -> 2506984 bytes Panels/title_test.scad | 27 Panels/title_test.stl | Bin 0 -> 44015 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod delete mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_Mask.gbr create mode 100644 Fireball/Fireball.kicad_pcb create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Push_button_A-5050.kicad_mod delete mode 100644 Schematics/SynthMages.pretty/SOCKET_2_PIN_Header.kicad_mod create mode 100755 VCO_MANUAL_v2.pdf