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BackGlide checkpoint before getting really weird with WireIt A couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke 3583986e89 Finished PCB, passes all passable DRCs created pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request 'new_footprints' (#5) from new_footprints into main v1 Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board facet normal 0.000000e+00 -3.662866e-15 1.000000e+00 vertex -9.435317e+01 1.041514e+02 4.255000e+01 facet normal -4.720703e-001 8.093055e-001 3.495342e-001 vertex 2.767200e+000 -3.118772e+000 2.480400e+001 facet normal -0.0419816 0.554754 0.830954 vertex -7.31983 0.636408 7.07423 facet normal -6.727979e-001 7.398263e-001 0.000000e+000 vertex 6.917118e+000 -3.993600e+000 0.000000e+000 facet normal 0.115828 -5.30788e-07 -0.993269 facet normal 0.247465 0.963808 0.0991679 facet.
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