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BackSMD Checkpoint after tweaking footprints some more, starting over at 14hp Checkpoint after tweaking footprints some more, starting over at 14hp Added hard sync to schematic, laid out PCB with exploratory 8hp layout PSU/Synth Mages Power Word Stun.kicad_pcb The Power Word Stun.kicad_pro "filename": "Synth Mages Power Word Stun.kicad_pcb group "" (id efdac9a8-63a2-4056-9007-59528f4494a3 Latest commits for file Fireball/Fireball.kicad_pcb tweaks layout with input from sam Latest commits for branch pcb_finalization re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1 delete mode 100644 Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod From 5663c8bc865b744661cf82b1abfca64d73c0f2fa Mon Sep 17 00:00:00 2001 Subject: [PATCH 06/13] add pic 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 move bugs to md file to be able to add picture 9f9f6acf76 Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops Compare 27 commits » 33729ec97f More repo cleanup, adopt github .gitignore file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file again gets comfier with gitignore and git rm --cache learns about gitignore and git rm --cache 19116ba39d Apply jlcpcb's design rules, small fixes for those couple more minor clearance tweaks couple more GND-stitch vias Latest commits for branch bugfix/v1.1 Add position for resistor between coarse and +12V, value Fireball/Fireball.kicad_sch | 120 Fireball/fp-info-cache | 23 (format (units 3) (units_format 1) (precision 4 style (thickness 0.15) (arrow_length 1.27) (text_position_mode 0) (extension_height 0.58642) (extension_offset 0.5) keep_text_aligned format (units.
- Normal 1.605954e-001 -2.740493e-001 9.482120e-001 vertex -3.530305e+000 2.787774e+000.
- -4.143483e-16 1.452521e-15 -1.000000e+00 facet normal -0.257269 -0.262733 0.929938.