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BackSchematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 2cddc4d62d38c9e1b69839f92a19e7915eecbceb 5ff3077e8252367b7eceb0b21b0803904b695d42 744b72ef7e0d94fccfae99ec3cb3514981ac4616 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for file .gitignore Initial commit README.md | 8 | 1N4148 | 100V 0.15A standard switching diode, DO-35 | | | | Q1, Q2, Q3 | 3 | 10uF | Polarized capacitor | | | | | | | | | | | R5 | 1 | LED | Light emitting diode, 5 mm LED 5 mm Small Signal NPN Transistor, TO-92 | | | | | R24, R26, R28 | 3 | 100R | Resistor | | Tayda | A-805 | | 4 | 47k | Resistor | | | .
- 5.902027e+000 9.983999e+000 vertex 7.057426e+000 7.134280e-001 9.983999e+000 vertex.
- -3.03882 -3.62229 21.7538 facet normal.
- -5.336789e-15 1.000000e+00 facet normal -4.792339e-001 -8.386592e-001 2.588158e-001 facet.
- 4.917467e-003 5.735575e-001 facet normal.
- Input and send reset to clk_inh.