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Back0) hide From d48d677c9103ec90137a6830434841a576342e9a Mon Sep 17 00:00:00 2001 Subject: [PATCH 07/13] Update Schematics/schematic_bugs_v1.md Clock POT is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v max // gate out (j4/j10 // clock in (j2/j11) // casc out (j14/j15) // reset/casc in (j1/j13) // gate out (j4/j10.