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... Finish schematic, add PDF Features already done: Internal clock with manual control. - Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and Reset In socket Reset Socket to U3-3 = capacitor measurement roughly 15nF (has a resistor footprint between +12V and Reset In - ~27K to U3-8? No, transistors maybe activate? Clock Out - 1K to U3-7 Glide section not working right, just pegging the output jacks Subject: [PATCH 13/13] re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md Clock POT is too small; need more than 100k to get below 200bpm~ From a5c5ff12ce18fecaaf346f973863d12bf361ac82 Mon Sep 17 00:00:00 2001 Subject: [PATCH] add pic 325d28022a Update current state of project. Add correct footprints to fireball Merge pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs created pull request 'Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 580484 bytes .../Panels/Radio_shaek_standoff_padded.stl | Bin 0 -> 2510902 bytes create mode 100644 Panels/FireballSpellVertVerySmall.png create mode 100755 Panels/FireballSpell.png create mode 100644 Schematics/SynthMages.pretty/Alpha Rotary 12.kicad_mod 46 lines From 4ee68877235c53d350cd6d734e74936e7f605c70 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file 55ee65a5e9 Checkpoint after tweaking footprints some more, starting over at 14hp Checkpoint after converting most things to SMD Binary files /dev/null and b/Panels/Font files/Quentincaps.ttf differ Binary files /dev/null and b/Panels/FireballSpell_Large_bw.xcf differ From f50bb0019af1e23a68a47e827989c11465d543f5 Mon Sep 17 00:00:00 2001 Subject: [PATCH 11/18] Add a front-panel PCB More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", From a924f971822abf6232c3be63abeee0abf33f42cb Mon Sep 17 00:00:00 2001 Subject: [PATCH] updates to rev 2.

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