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As: Update README.md README.md | 1 | | AR Path="/607F01E7" Ref="R?" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/607ED812/607F01E7" Ref="R25" Part="1" AR Path="/60B160FF" Ref="J?" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/607ED812/60B16110" Ref="J11" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/607ED812/60A9C088" Ref="R30" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/607ED812/60802B98" Ref="R29" Part="1" AR Path="/607ED812/60B16110" Ref="J8" Part="1" AR Path="/60A9C0A9" Ref="R?" Part="1" AR Path="/60C38343" Ref="R?" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/60802B98" Ref="R?" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/60802B98" Ref="R?" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 Subject: [PATCH] gets comfier with gitignore and git rm --cache 269f3bf9f9 power word stun initial commit by { "board": { More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file f6c7924538 Messing around with panel title fonts 62cb30efbf Initial kicad, images, gitignore for kicad backups From f835c1b52669c83e3b7ee8bb7127766f514de308 Mon Sep 17 00:00:00 2001 Subject: [PATCH] glide fix a5c5ff12ce18fecaaf346f973863d12bf361ac82 Notes from debugging Latest commits for file Images/PXL_20210831_001017829.jpg Period: 1 week 1 day 1 day Trim 5mm from vertical for both panels, to make fitting inside a case easier. Or 10mm if it can fit; losing the bodge area. Outs: Clock Out - 1K to U2-14 Case Out - Diode from rotary pin 13? CV Out - 1K to TP5 Gate Out - 1K to U3-7 PSU/Synth Mages Power Word Stun Panel.kicad_pro 4ee6887723 Add some perfboard sections, power headers, teardrops .../Unseen Servant/Unseen Servant.kicad_sch | 166 Add position for resistor between coarse and +12V, value unknown Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground Fireball/Fireball.kicad_pro | 93 Fireball/Fireball.kicad_sch .

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