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Back13:39:59 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#5 Merge pull request 'Put title box in PDF export' (#4) from schematic by Eeschema.
- -0.0096566 0.0980067 0.995139 vertex.
- 1924143 16A (HC Generic Phoenix Contact connector.
- 4.2532 5.60181 7.5827 vertex 4.13797 -5.40019.
- Vertical, 5 rows 32.