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B.Net" condition "A.Type == 'via'" (condition "A.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request synth_mages/MK_VCO#4 24955050f1 Merge pull request synth_mages/MK_VCO#3 From 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Wondermark fix.

0.195093 -0.980785 -1.68839e-05 facet normal 0.0846382.
Pins: 13; pin pitch: 5.08mm; Angled; threaded flange.
Vertex -4.261518e+000 2.411432e+000 2.496000e+001 vertex -5.631111e+000 3.382432e-001 2.496000e+001.
3.993601e+000 0.000000e+000 facet normal -0.652551 0.754471 0.0703597.

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