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BackFront L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Image of caxia score 531ebcae92 Add html test version b22080a808 More experimentation with panel title fonts Untested hardware and software — Do not assume anything works!** Latest commits for file Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod Latest commits for file Panels/FireballSpell_Large_bw.xcf Panels/10_step_seq.scad Normal file Unescape Latest commits for file VCO_MANUAL_v2.pdf 2015-02-23 19:36:11 -0800 08c0726655 2015-02-23 04:32:30 -08:00 main MK_SEQ/Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_pcb Normal file Unescape Mon 19 Apr 2021 10:22:18 AM EDT Mon 10 May 2021 12:33:34 AM EDT