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This page is to collect findings from researching other potential fab plants. Our standard design is the decade counter with internal clock rate. One potentiometer for internal clock signal (possibly external). Commonly called a "Baby 8". Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF | J6 | 1 | TL074 | Quad Low-Noise JFET-Input Operational Amplifiers, DIP-8/SOIC-8/TO-99-8 | | J2 | 1 | | C2, C5, C6, C8, C9, C11, C12; space accordingly Move any UX connections.

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