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BackLines Notes from debugging Clock POT is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings Add splits and labels to get an idea how to switch modes. PRs welcome. I think this is good practice, but ho-dang what a mess From 7022ad9ddb43c592e11528a5ae21edf443c088e4 Mon Sep 17 00:00:00 2001 Subject: [PATCH 12/13] Update Schematics/schematic_bugs_v1.md
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