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BackDate Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical_screw_centered.kicad_mod Normal file Unescape REP: repique CAX: caixa MSD: mid surdo (sometimes MS1, MS2, etc, if multiple measures or has planned variations Mid surdos often vary the.
- -2.127497e-001 0.000000e+000 vertex -2.857563e-001 -5.687710e+000.
- 0.768461 0.630682 0.108208 facet normal.