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Back20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More repo cleanup, adopt github .gitignore file More repo cleanup, adopt github .gitignore file More repo cleanup, adopt github .gitignore file .gitattributes | 2 Latest commits for file Schematics/bad_trace_v1.jpeg add pic add pic add pic add pic Schematics/bad_trace_v1.jpeg | Bin 0 -> 2506984 bytes Panels/title_test.scad | 22 .../precadsr_aux_Gerbers/precadsr-job.gbrjob | 128 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 4 .../PCB/precadsr_aux_Gerbers/precadsr-PTH.drl | 22 Panels/title_test.stl | Bin 0 -> 170624 bytes README.md | 8 "use_height_for_length_calcs": true From 01bb4964a63ffeda0774c500204d2687e8f4164c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Documentation Docs/build.md | 4 | 47k | Resistor | | | | C2 | 1 | 10R | Resistor | | | | Tayda | A-804 | | C7, C12, C13 | 3 From 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Added input resistor for sync; placed everything on PCB 7f9b624c8e tweaks layout with input from sam tweaks layout with input from sam Latest commits for file Images/capsocket.png b554ec2138 Add footprint items for panel holes; separate panel and Pin.
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