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Receptacle horizontal through-hole USB type A, right angle USB type A right angle (http://www.molex.com/pdm_docs/sd/483930003_sd.pdf USB 3.0 3.1 3.2 4.0 Type-C receptable, through-hole mount, SMD, right-angle (http://www.molex.com/pdm_docs/sd/473460001_sd.pdf Micro B horizontal USB Micro-B receptacle, horizontal, SMD, 10118193, without flange, https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10118193.pdf Dustproof Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330001_sd.pdf Micro-USB SMD Typ-B Vertical Molex Vertical Micro USB Type C, Right Angle, Surface Mount, ZIF, Bottom Contact FFC/FPC, 200528-0110, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator Soldered wire connection with feed through strain relief, for 5 mm | | C1, C11 | 2 | 10k | Resistor | | | | Tayda | A-1121 | | | | | | | R21, R22, R23 | 3 | 1nF | Film capacitor | | Tayda | A-001 | | S1 | 1 | LM358 | Low-Power, Dual Operational Amplifiers, DIP-14/SOIC-14 | | S1 | 1 | B10k | Potentiometer | | S3 | 1 Hardware/lib/aoKicad | 1 uF tantalum\nYuSynth 1, 10 µF tantalum.\nMFOS 1, 1+15 µF electrolytic.\n1 µF tanty looks better than EL\n(higher output, less leakage)\nbut only by a little. 1 µF \npolyester film looks much \nbetter. F0 "Pots, switches, misc" 50 Optional SIP socket for\nsocketing capacitors C13 marked 1 nF\non first run PCBs as 1 nF. It should be 10 nF. Documentation ## Mechanical assembly Documentation # ---> KiCad # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.zip *.DS_Store *~ .gitignore-extra *.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add PSU Add PSU Add PSU Add PSU Add PSU PSU/PSU.md | 5 | 22k | Resistor | | C6, C7, C8, C9 | 4 .../precadsr_panel_al.kicad_pcb | 2707 .../Bigger_Push_Switch_Hole.kicad_mod | 17 .../PCB/precadsr_Gerbers/precadsr-PTH.drl | 207 .../PCB/precadsr_Gerbers/precadsr-job.gbrjob | 2 | 1N5817 | Schottky diode | Tayda | A-004 | | | | S3 | 1 | B10k | Potentiometer | | | | C3, C4, C5 | 2 | 10k | Resistor | | R25, R27, R29 | 3 pin Molex.

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