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Back[ ird*cos(lf0), ird*sin(lf0), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92