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Vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf SSO Stretched SO SOIC Pitch 1.27 SSOP-8 2.9 x2.8mm Pitch 0.65mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf HSOP 11.0x15.9mm Pitch 0.65mm HSOP 11.0x15.9mm Pitch 1.27mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf HSOP, 32 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation DD), generated with kicad-footprint-generator Molex Mini-Fit Sr. Power Connectors, 43915-xx12, 6 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator connector Molex Nano-Fit Power Connectors, 42820-32XX, With thermal vias in pads.

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