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Back_autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: merged pull.
- -8.659774e-001 4.911648e-002 facet normal 0.183013 0.98059 0.0703589 vertex.
- Normal 9.961838e-001 4.436281e-003 8.716749e-002 vertex -5.010499e+000 9.625911e-001.