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Back"Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Paste" "Notes": "Layer B.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer F.SilkS" "Notes": "Layer B.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 2cddc4d62d38c9e1b69839f92a19e7915eecbceb formatting caixa bits formatting caixa bits c9e81f0cc6 Image of caxia score caixa_sr1.png | Bin 26014376 -> 26031216 bytes // Width of module (HP) width = 14; // [1:1:84] /* [Holes] */ // // Whether to create cutouts around the outer circumference of the shaft notch (if it is machine-specific data Forget (and ignore) fp-info-cache file as it is if your 3PDT toggle switch, like mine, is a ceramic 104 power cap like C5, C6, C8, C9 | 1 | LM358 | Low-Power, Dual Operational Amplifiers, DIP-8/SOIC-8/TO-99-8"/>