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*-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Images/capsocket.png | Bin 0 -> 104908 bytes Panels/title_test.scad | 22 Hardware/PCB/precadsr/precadsr.sch | 247 (40 Dwgs.User user hide (0 "F.Cu" signal (31 "B.Cu" signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 "F.Paste" user (36 "B.SilkS" user "B.Silkscreen" 37 "F.SilkS" user "F.Silkscreen" (38 "B.Mask" user (39 F.Mask user (40 Dwgs.User user hide (42 Eco1.User user (43 Eco2.User user (44 Edge.Cuts user (45.

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