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Module pot_wh148() { module v_wall(h, l, wall_thickness); Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane Latest commits for file sr1_full.png From 1e6cc98f413992554cb33b458eea58dbb7544fc2 Mon Sep 17.

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