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Or impractical: - CV-controlled clock. Presumably the CV in to pause the sequence. Seven-segment display. Can be done, but requires a lot of wiring and increases risk of noise on power rails. Latest commits for branch hard_sync Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main ... Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 11692 bytes .../Panels/HOLD PORTAL.png | Bin 0 -> 167187 bytes Images/PXL_20210831_002553634.jpg | Bin 0 -> 167187 bytes Images/PXL_20210831_002553634.jpg | Bin 0 -> 10174 bytes .../PRISMATIC SPHERE.png | Bin 0 -> 23847 bytes Panels/FireballSpell_Large.webp | Bin 0 .

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