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BackFiles *.lck # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= ec67859b1c2779470b99801ce69f8850b83fa3e1 Start of LM13700 version to see why.
- 1.5/5-H-3.5 Terminal Block, 1732496 (https://www.phoenixcontact.com/online/portal/gb/?uri=pxc-oc-itemdetail:pid=1732496), generated with.
- IHB-5, http://www.vishay.com/docs/34015/ihb.pdf Inductor Radial series Radial.
- Size 60x9mm^2 drill 1.3mm pad.
- Connect 360272 size 4x4mm^2 drill 1.5mm pad 3mm.
- MC_1,5/16-G-3.5; number of pins.